Hardware-Software Codesign · Systems Architecture Document SA-001
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Status

This page shows my current work.

  • spacetetris audit: I do a strict audit of the code against MISRA C:2012 and JPL Power of 10. I now divide the physics core from the platform I/O.
  • Real-time FPGA trade engine: I help to make an FPGA order book (real-time-trader) that operates through UART. The target latency is less than 200 ns.
  • RTOS knowledge: I prepare the move of my embedded engine to the Flipper Zero.